Generalized ternary simulation of sequential circuits
RAIRO - Theoretical Informatics and Applications - Informatique Théorique et Applications, Special issue for Professor Karel Culik II : 60 th birthday, Tome 28 (1994) no. 3-4, pp. 159-186. 
@article{ITA_1994__28_3-4_159_0,
     author = {Seger, C.-J. and Brzozowski, J. A.},
     title = {Generalized ternary simulation of sequential circuits},
     journal = {RAIRO - Theoretical Informatics and Applications - Informatique Th\'eorique et Applications},
     pages = {159--186},
     publisher = {EDP-Sciences},
     volume = {28},
     number = {3-4},
     year = {1994},
     zbl = {0879.94040},
     language = {en},
     url = {http://archive.numdam.org/item/ITA_1994__28_3-4_159_0/}
}
TY  - JOUR
AU  - Seger, C.-J.
AU  - Brzozowski, J. A.
TI  - Generalized ternary simulation of sequential circuits
JO  - RAIRO - Theoretical Informatics and Applications - Informatique Théorique et Applications
PY  - 1994
SP  - 159
EP  - 186
VL  - 28
IS  - 3-4
PB  - EDP-Sciences
UR  - http://archive.numdam.org/item/ITA_1994__28_3-4_159_0/
LA  - en
ID  - ITA_1994__28_3-4_159_0
ER  - 
%0 Journal Article
%A Seger, C.-J.
%A Brzozowski, J. A.
%T Generalized ternary simulation of sequential circuits
%J RAIRO - Theoretical Informatics and Applications - Informatique Théorique et Applications
%D 1994
%P 159-186
%V 28
%N 3-4
%I EDP-Sciences
%U http://archive.numdam.org/item/ITA_1994__28_3-4_159_0/
%G en
%F ITA_1994__28_3-4_159_0
Seger, C.-J.; Brzozowski, J. A. Generalized ternary simulation of sequential circuits. RAIRO - Theoretical Informatics and Applications - Informatique Théorique et Applications, Special issue for Professor Karel Culik II : 60 th birthday, Tome 28 (1994) no. 3-4, pp. 159-186. http://archive.numdam.org/item/ITA_1994__28_3-4_159_0/

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